1. Field of the Invention
The present invention relates to a microprocessor having a reset function and, more particularly, to a microprocessor having a simple mechanism required to initialize a system, especially when used in a multiprocessor system.
The present invention also relates to a multiprocessor system having a simple mechanism for initializing the entire system.
2. Description of the Background Art
A microprocessor performs a reset action for initializing the inside of the processor in response to assertion of a reset signal from the exterior upon power-on for execution of a user program, for example. The reset action includes a hardware reset action wherein the reset signal asserted from the exterior of the microprocessor is applied to memory elements in the processor to reset the contents stored in the memory elements, and a software reset action wherein a program for reset fetched from an external memory is executed in the processor to allow the user program to be ready for processing. Particularly, in the software reset action, when the reset signal is asserted, a reset vector entry is fetched from the external memory, and information contained in the entry is referred to, whereby the program for reset is fetched.
In a multiprocessor system including a plurality of processors for performing the above described reset action in such a manner that one of the processors functions as a master processor while the others function as slave processors, all of the processors must be initialized to reset the entire system. For this purpose, the reset signal is initially asserted in all of the processors. A program for reset is previously stored in a read only memory (referred to hereinafter as a ROM) on the system. After assertion of the reset signal, each of the processors accesses the ROM to execute the program for reset, whereby each processor is initialized. Since the processors are not permitted to simultaneously access the ROM, the multiprocessor system is adapted such that the processors access the ROM in sequential order.
In the multiprocessor system constructed as above described, if the reset signal is simultaneously asserted in the processors, the processors are not permitted to simultaneously access the ROM which stores the reset vector entry in order to refer to the reset vector entry. Thus, a new complicated mechanism is required such as a bus adjustment circuit for causing the plurality of processors to sequentially access the ROM. Further, it is a customary practice that the respective processors execute different program routines in the program for reset because of a difference in reset contents between the master and slave processors. Then, there arises a need for a mechanism for identifying which processor is to execute each of the program routines.
An alternative attempt considered is such that a plurality of local ROMs are provided in corresponding relation to the respective processors in the multiprocessor system and each of the processors executes the instruction for reset stored in the corresponding ROM to perform the reset action. However, this attempt involves a need to provide to each processor address information for specifying which one of the ROMs is accessed by each processor after the assertion of the reset signal. To meet this requirement, separate reset vector entries are considered to be set for the respective processors. However, the use of identical processors as the master and slave processors necessitates the setting of address information indicating the ROMs to be accessed by the respective processors for the reset vector entries from the exterior. In both ways, a mechanism for setting the address information from the exterior must be additionally provided. Further, the provision of the plurality of ROMs corresponding to the respective processors increases the amount of hardware.
The multiprocessor system requires a complicated mechanism for controlling processing between units such as the master processor and the slave processors. The provision of the above described new mechanism causes a more complicated system structure, and a multiplicity of memories are required to function the multiprocessor system. Thus, the unnecessary increase in the number of memories is not desirable.
According to a first aspect of the present invention, a microprocessor comprises: a processing portion including an instruction decoder for decoding an instruction, the processing portion for performing various processes in accordance with a result of decoding from the instruction decoder to execute the instruction; an access control portion controlled by the processing portion for outputting an address specifying a memory area to apply the instruction stored in the memory area to the instruction decoder; and wherein memory elements in the microprocessor are reset in response to an external reset signal, and wherein, in a first mode, (i) a first interrupt process program is stored in the internal memory after completion of assertion of the reset signal, (ii) the processing portion controls the access control portion so that instructions constituting the first interrupt process program are applied to the instruction decoder in response to an interrupt signal applied to the processing portion, and (iii) the processing portion executes an instruction for reset among the instructions constituting the first interrupt process program applied to the instruction decoder, whereby the microprocessor is initialized.
Preferably, the microprocessor further comprises: an address terminal for outputting the address to the exterior, wherein the address terminal is in a high-impedance state in the first mode during the time between input of the reset signal and input of at least the interrupt signal.
Preferably, in the microprocessor, the access control portion outputs an information signal to the processing portion in response to a request from the processing portion that the access control portion should perform an access to the exterior of the microprocessor when the address terminal is in the high-impedance state, the information signal providing information about prohibition of the access.
Preferably, the microprocessor further comprises: an internal memory; and an internal data bus for establishing a connection between the internal memory and the processing portion, wherein the access control portion outputs the address to the internal memory so that the first interrupt process program is applied from the internal memory through the internal data bus to the instruction decoder.
According to a second aspect of the present invention, the microprocessor of the first aspect further comprises: mode setting means for setting the microprocessor in one of the first mode and a second mode, wherein, in the second mode, (iv) the processing portion controls the access control portion so that instructions constituting a reset process program are applied to the instruction decoder in response to the reset signal applied to the processing portion, (v) the processing portion executes the instructions of the reset process program applied to the instruction decoder, whereby the microprocessor is initialized, and (vi) interrupt data on which the interrupt signal is based are produced.
Preferably, in the microprocessor, the access control portion outputs the address to external memory means so that the reset process program stored in the external memory means is fetched and applied to the instruction decoder when the second mode is set.
Preferably, in the microprocessor, further comprising an internal memory and in the second mode, (vii) the reset process program is executed whereby a second interrupt process program is stored in the internal memory after completion of assertion of the reset signal.
Preferably, in the microprocessor, the first interrupt process program includes a process in accordance with a factor of the interrupt signal.
According to a third aspect of the present invention, a microprocessor comprises: first and second processing portions each including an instruction decoder for decoding an instruction, each of the first and second processing portions for performing various processes in accordance with a result of decoding from the instruction decoder thereof to execute the instruction; an access control portion controlled by the first and second processing portions for outputting an address specifying a memory area to apply the instruction stored in the memory area to the instruction decoder of one of the first and second processing portions; and an internal memory reset in response to an external reset signal, wherein the first processing portion controls the access control portion so that instructions constituting a reset process program are applied to the instruction decoder of the first processing portion in response to the reset signal applied to the first processing portion, wherein the first processing portion executes the reset process program applied to the instruction decoder thereof, whereby the first processing portion is initialized, wherein the second processing portion controls the access control portion so that instructions constituting a first interrupt process program are applied to the instruction decoder of the second processing portion in response to an interrupt signal applied to the second processing portion, wherein the second processing portion executes an instruction for reset among the instructions constituting the first interrupt process program applied to the instruction decoder thereof, whereby the second processing portion is initialized, and wherein the first processing portion executes the reset process program to produce and apply the interrupt signal to the second processing portion.
Preferably, in the microprocessor, the reset process program is executed whereby the first interrupt process program and a second interrupt process program for an interrupt process of the first processing portion are stored in the internal memory.
Preferably, the microprocessor further comprises: an internal data bus through which the first interrupt process program stored in the internal memory is applied to the instruction decoder of the second processing portion.
Preferably, in the microprocessor, the access control portion outputs the address to external memory means so that the reset process program stored in the external memory means is fetched and applied to the instruction decoder of the first processing portion.
Preferably, the microprocessor further comprises: an internal data bus for establishing respective connections between the internal memory and the first and second processing portions, wherein the access control portion outputs the address to the internal memory so that the first interrupt process program stored in the internal memory is applied through the internal data bus to the instruction decoder of the second processing portion.
Preferably, in the microprocessor, the first interrupt process program includes a process in accordance with a factor of the interrupt signal.
According to a fourth aspect of the present invention, a multiprocessor system comprises first and second microprocessors, each of the first and second microprocessors comprising: a processing portion including an instruction decoder for decoding an instruction, the processing portion for performing various processes in accordance with a result of decoding from the instruction decoder to execute the instruction; an access control portion controlled by the processing portion for outputting an address specifying a memory area to apply the instruction stored in the memory area to the instruction decoder; and an internal memory reset in response to a reset signal applied thereto, wherein the processing portion of the first microprocessor controls the access control portion of the first microprocessor so that instructions constituting a reset process program are applied to the instruction decoder of the first microprocessor in response to the reset signal applied to the first microprocessor, wherein the processing portion of the first microprocessor executes the instructions of the reset process program applied to the instruction decoder thereof, whereby the first microprocessor is initialized, wherein an interrupt signal is produced on the basis of execution of the reset process program, wherein the processing portion of the second microprocessor controls the access control portion of the second microprocessor so that instructions constituting a first interrupt process program are applied to the instruction decoder of the second microprocessor in response to the interrupt signal applied to the second microprocessor, and wherein the processing portion of the second microprocessor executes an instruction for reset included in the first interrupt process program applied to the instruction decoder thereof, whereby the second microprocessor is initialized.
Preferably, the multiprocessor system further comprises: memory means for storing the reset process program, wherein the access control portion of the first microprocessor outputs the address to the memory means so that the first microprocessor fetches the reset process program from the memory means to execute the reset process program, wherein the internal memory of the second microprocessor stores the first interrupt process program, and wherein the access control portion of the second microprocessor outputs the address to the internal memory of the second microprocessor so that the first interrupt process program is applied from the internal memory of the second microprocessor to the instruction decoder of the second microprocessor.
Preferably, in the multiprocessor system, the memory means further stores the first interrupt process program; the first microprocessor performs the reset process program to transfer the first interrupt process program from the memory means to the internal memory of the second microprocessor; and the second microprocessor further comprises an internal data bus through which the first interrupt process program stored in the internal memory of the second microprocessor is applied to the instruction decoder of the second microprocessor.
Preferably, in the multiprocessor system, the second microprocessor further comprises an address terminal for outputting the address; and the address terminal is in a high-impedance state during the time between input of the reset signal and input of at least the interrupt signal.
Preferably, in the multiprocessor system, the reset process program is executed whereby the first interrupt process program and a second interrupt process program for an interrupt process of the processing portion of the first microprocessor are stored in the internal memories of the second and first microprocessors, respectively.
Preferably, in the multiprocessor system, the first interrupt process program includes a process in accordance with a factor of the interrupt signal.
In accordance with the microprocessor of the first aspect of the present invention, as above described, the memory elements in the microprocessor are reset in response to the external reset signal. In the first mode, the instructions constituting the first interrupt process program are applied to the instruction decoder in response to the input of the interrupt signal, and the processing portion executes the instruction for the reset process included in the interrupt process program, which causes initialization. Thus, if the microprocessor constitutes a multiprocessor system with another processor which is initialized by execution of the instruction in response to the reset signal, the conventional mechanism originally provided for the interrupt process may be utilized to allow the execution of the instruction for initialization. It is not necessary to add to the respective processors a hardware mechanism for identifying which memory area storing the program routine to be executed by the respective processors is to be accessed. This facilitates the system design of the multiprocessor system as compared with the system wherein the programs are executed in response to a common reset signal.
In accordance with the microprocessor of the second aspect of the present invention, in the second mode, the instructions constituting the reset process program are applied to the instruction decoder of the processing portion in response to the reset signal applied to the processing portion, and the processing portion executes the instructions of the reset process program, whereby the microprocessor is initialized. When a processor set in the first mode and a processor set in the second mode are provided to constitute a multiprocessor system, the whole system may be initialized without providing in the respective processors the hardware mechanism for identifying which memory area storing the program routine to be executed by the respective processors is to be accessed, as compared with the system wherein the processors execute programs in response to the common reset signal. In this case, the identical processors should be provided except the change of the modes.
In accordance with the microprocessor of the third aspect of the present invention, the internal memory in the microprocessor is reset in response to the external reset signal. The first processing portion is initialized by the execution of the reset process pogrom in response to the input of the reset signal. The second processing portion is initialized by the execution of the instruction for the reset process included in the interrupt process program in response to the input of the interrupt signal. It is not necessary to provide in the microprocessor a hardware mechanism for identifying which memory area storing the program routine to be executed by the respective processors is to be accessed. This facilitates the design of the microprocessor as compared with the system wherein the processors execute programs in response to a common reset signal.
In accordance with the multiprocessor system of the fourth aspect of the present invention, in the first microprocessor, the instructions constituting the reset process program are applied to the instruction decoder of the first microprocessor in response to the input of the reset signal, and the instructions of the reset process program are executed, whereby the first microprocessor is initialized and the interrupt signal is produced. In the second microprocessor, the instructions constituting the interrupt process program are applied to the instruction decoder of the second microprocessor in response to the input of the interrupt signal, and the instruction for reset included in the interrupt process program is executed, whereby the second microprocessor is initialized. This allows the second microprocessor to execute the instruction for initialization by utilizing the conventional mechanism originally provided for the interrupt process. It is not necessary to add to each of the first and second microprocessors a hardware mechanism for identifying which memory area storing the program routine to be executed by the respective processors is to be accessed. This facilitates the system design of the multiprocessor system as compared with the system wherein the first and second microprocessors execute programs in response to a common reset signal.
It is therefore a primary object of the present invention to provide a microprocessor for use in a multiprocessor system and including a simple mechanism required to initialize the multiprocessor system.
It is another object of the present invention to provide a multiprocessor system having a simple mechanism for resetting the entire system by using such a microprocessor.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.